(a) Field of the Invention
The present invention relates to a metal-oxide-silicon (MOS) transistor and a manufacturing method thereof. More particularly, the present invention relates to a MOS transistor and a manufacturing method thereof for suppressing channel hot carrier (CHC) degradation.
(b) Description of the Related Art
FIG. 1 is a cross-sectional view showing a typical MOS transistor.
Referring to FIG. 1, a gate insulation layer 110 and a gate electrode layer 120 are sequentially accumulated on a channel region 102 in a semiconductor substrate 100 such as a silicon substrate. An oxide layer 130 is formed on sidewalls of the gate electrode layer 120, and a capping oxide layer 140 and a gate spacer layer 150 are formed thereon. The capping oxide layer 140 is also formed on a part of the surface of the semiconductor substrate 100. A deep source/drain region 162 and an extended region 161 thereof for forming a lightly doped drain (LDD) structure are formed on a predetermined region of the semiconductor substrate 100.
In such a typical structure of a MOS transistor, the extended region 161 of the source/drain has a shallow junction depth and is formed in order to suppress channel hot carrier (CHC) degradation. However, an increase of a hot carrier concentration in the channel region 102 according to the shallow junction depth thereof may cause difficulty in suppressing the CHC degradation. The increase of a hot carrier concentration in the channel region causes damage to an interface of metal-oxide-silicon (MOS), and thus a voltage-current characteristic of the MOS transistor may be deteriorated.
The above information described in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute prior art.